The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a multilayer interconnection structure.
Conventionally, increase of operational speed has been attempted in semiconductor devices by way of device miniaturization according to the scaling law. On the other hand, in recent semiconductor integrated circuits of high integration density, it is insufficient to use a single interconnection layer for wiring semiconductor devices of enormous numbers formed on the substrate, and thus, a multilayer interconnection structure in which a number of interconnection layers are stacked with intervening insulation films is used generally for providing the necessary interconnection.
In the semiconductor integrated circuit having such a multilayer interconnection structure, on the other hand, it is practiced to provide an anti-moisture guard ring (referred to hereinafter simply as “guard ring”) along a periphery of a chip so as to block penetration of moisture or gas. Such a guard ring extends in the multilayer interconnection structure continuously along the periphery of the chip and interrupts the penetration path of moisture or gas, which may be formed at the interface between an interlayer insulation film and an interconnection layer.
FIGS. 1A and 1B show the construction of a semiconductor integrated circuit 10 having such a conventional guard ring, wherein FIG. 1A is a cross-sectional view of the foregoing semiconductor integrated circuit 10 including a guard ring 1, while FIG. 1B is a plane view showing the entirety of the chip of the semiconductor integrated circuit 10.
Referring to FIG. 1A, the semiconductor integrated circuit 10 is formed on a device region 11A defined on a Si substrate 11 by a device isolation structure 11B and includes active devices such as a MOS transistor formed on the device region 11A.
The semiconductor integrated circuit 10 includes a first multilayer interconnection structure 12 formed on the substrate and includes therein interconnection layers L1-L4 and via-plugs P1-P6 and a second multilayer interconnection structure 13 formed on the first multilayer interconnection structure 12, wherein the second multilayer interconnection structure 13 includes therein interconnection layers L5-L7 and via-plugs P7 and P8. In FIG. 1, it should be noted that illustration of the interlayer insulation films in the multilayer interconnection structures 12 and 13 is omitted.
Further, as shown in the plan view of FIG. 1B, a guard ring 14 is formed on the substrate 11 continuously along the periphery of the chip.
Referring to FIG. 1A again, the guard ring 14 is formed by stacking conductor patterns C1-C7 extending continuously along the periphery of the chip respectively in correspondence to the interconnection layers L1-L7 and conductor walls W1-W7 also extending continuously along the periphery of the chip respectively in correspondence to plugs P1a and P1b and also the plugs P2-P7.
Such a guard ring 14 has a layered structure corresponding to the multilayer interconnection structures 12 and 13 and thus can be formed at the time of formation of the multilayer interconnection structure by a common process.